EDN - Voice of the Engineer
WEB1 day ago · partner content. In this podcast episode, Sally talks to 4DS’ Peter Himes about the company’s ReRAM persistent memory and much more. Electronic Design News (EDN) is an electronics community for engineers, by engineers. Find the latest articles, magazines, tools, and blogs in the industry.
USB Type-C PD 3.0 Specification, Charging and Design - EDN
WEBJun 25, 2021 · The first one—Power Delivery 2.0—supports fixed output voltages including 5, 9, 12, 15, or 20V at specific operating currents, for example 3 A. The second specification—PD 3.0—includes programmable power supply (PPS), a feature that allows the USB Type-C charger’s output voltage to be adjusted in …
Setup and Hold Time Basics - EDN
WEBApr 19, 2012 · Hold time is defined as the minimum amount of time after the clock’s active edge during which data must be stable. Violation in this case may cause incorrect data to be latched, which is known as a hold violation. Note that setup and hold time is measured with respect to the active clock edge only.
Eye Diagram Basics: Reading, Analyzing and Applying
WEBDec 16, 2011 · An eye diagram is a common indicator of the quality of signals in high-speed digital transmissions. An oscilloscope generates an eye diagram by overlaying sweeps of different segments of a long data stream driven by a master clock. The triggering edge may be positive or negative, but the displayed pulse that appears after a delay period may go ...
Roadside Electric Car Charging: 3 Solutions For EVs - EDN
WEBOct 27, 2020 · Three modules (66 kg): 10.5 kWh (9.6 kWh usable) for 42-45 miles of range. Four modules (88 kg): 14 kWh (12.8 kWh usable) for 56-60 miles of range. Five modules (110 kg): 17.5 kWh (16 kWh usable) for 70-75 miles of range. Figure 2 By allowing uses to set the modularity, the SparkCharge unit can fit the available space in roadside-service ...
Setup and Hold Time Equations and Formulas - EDN
WEBAug 10, 2012 · Hence to fulfill the setup time requirement, the formula should be like the following. T c2q + T comb + T setup ≤ T clk + T skew (1) Let’s have a look at the timing diagram below to have a better understanding of the setup and hold time. Figure 2 Setup and hold timing diagram. Now, to avoid the hold violation at the launching flop, the data ...
Audio levels, dBu, dBV, and the gang: What you need to know
WEBApr 18, 2017 · Simply, they refer to the voltage levels defined as 0 dBVU. Unbalanced The standard consumer “-10dBV” standard means that 0 dBVU equals -10 dBV, or, using the dB-to-volts formula: = 1V • 10 (-10/20) = 316.2 mV. It so happens that this interface has been defined to carry 2V maximum (sine RMS, or 5.66 V P-P ).
Equalization Techniques: CTLE, DFE, FFE, and Crosstalk - EDN
WEBOct 21, 2015 · DFE (decision feedback equalization) uses a decision circuit as part of its feedback loop. CTLE technology doesn’t change for PAM4 signaling. Tx FFE doesn’t change in principle, though with four different symbol levels, it changes in practice. But with four distinct “decisions” to feed back to the decision circuit, DFE differs for PAM4.
Understanding grounding, shielding, and guarding in high ... - EDN
WEBFebruary 15, 2013. by James Niemann. Comment 1. Advertisement. Inadequate shielding and bad grounding are often blamed when measurements are inaccurate, especially in high-impedance applications. In fact, shielding and grounding problems are frequently responsible for measurement errors, but many test …
A guide to using FETs for voltage controlled circuits, Part 1
WEBOct 13, 2017 · The answer is yes (e.g., VCR11), but it turns out that virtually any other FET (e.g., JFET and MOSFET) can be used as a voltage controlled resistor. Basic voltage controlled resistor (VCR) circuits. One of the simplest uses of a voltage controlled resistor is an electronically controlled attenuator or “volume control”.